

module Integrator
    #(
        parameter IWID = 12,
        parameter OWID = 32
    )
    (
        input wire signed [IWID-1:0] i_SigIn,
        input wire i_clk,
        input wire i_rst,
        output reg signed [OWID-1:0] o_sum
    );


    always@(posedge i_clk or posedge i_rst) begin
        if(i_rst) begin
            o_sum<='b0;
        end
        else begin
            o_sum<=o_sum+i_SigIn;
        end
    end

endmodule

